VHDL Tutorial : Intoduction

What Is VHDL?

   VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system, or anything in between. The digital system can also be described hierarchically. Timing can also be explicitly modeled in the same description.

   The VHDL language can be regarded as an integrated amalgamation of the following languages:

sequential language +

concurrent language +

net-list language +

timing specifications +

waveform generation language => VHDL

   Therefore, the language has constructs that enable you to express the concurrent or sequential behavior of a digital system with or without timing. It also allows you to model the system as an interconnection of components. Test waveforms can also be generated using the same constructs. All the above constructs may be combined to provide a comprehensive description of the system in a single model.

   The language not only defines the syntax but also defines very clear simulation semantics for each language construct. Therefore, models written in this language can be verified using a VHDL simulator. It is a strongly typed language and is often verbose to write. It inherits many of its features, especially the sequential language part, from the Ada programming language. Because VHDL provides an extensive range of modeling capabilities, it is often difficult to understand. Fortunately, it is possible to quickly assimilate a core subset of the language that is both easy and simple to understand without learning the more complex features. This subset is usually sufficient to model most applications. The complete language, however, has sufficient power to capture the descriptions of the most complex chips to a complete electronic system.

   

History

   The requirements for the language were first generated in 1981 under the VHSIC program. In this program, a number of U.S. companies were involved in designing VHSIC chips for the Department of Defense (DoD). At that time, most of the companies were using different hardware description languages to describe and develop their integrated circuits. As a result, different vendors could not effectively exchange designs with one another. Also, different vendors provided DoD with descriptions of their chips in different hardware description languages. Reprocurement and reuse was also a big issue. Thus, a need for a standardized hardware description language for design, documentation, and verification of digital systems was generated.

A team of three companies, IBM, Texas Instruments, and Intermetrics, were first awarded the contract by the DoD to develop a version of the language in 1983. Version 7.2 of VHDL was developed and released to the public in 1985. There was a strong industry participation throughout the VHDL language development process, especially from the companies that were developing VHSIC chips. After the release of version 7.2, there was an increasing need to make the language an industry-wide standard. Consequently, the language was transferred to the IEEE for standardization in 1986. After a substantial enhancement to the language, made by a team of industry, university, and DoD representatives, the language was standardized by the IEEE in December 1987; this version of the language is now known as the IEEE Std 1076-1987. The official language description appears in the IEEE Standard VHDL Language Reference Manual made available by the IEEE. The language described in this book is based on this standard. The language has since also been recognized as an American National Standards Institute (ANSI) standard.

The Department of Defense, since September 1988, requires all its digital Application-Specific Integrated Circuit (ASIC) suppliers to deliver VHDL descriptions of the ASICs and their subcomponents, at both the behavioral and structural levels. Test benches that are used to validate the ASIC chip at all levels in its hierarchy must also be delivered in VHDL. This set of government requirements is described in military standard 454.

Capabilities

    The following are the major capabilities that the language provides along with the features that differentiate it from other hardware description languages.

• The language can be used as an exchange medium between chip vendors and CAD tool users. Different chip vendors can provide VHDL descriptions of their components to system designers. CAD tool users can use it to capture the behavior of the design at a high level of abstraction for functional simulation.

• The language can also be used as a communication medium between different CAD and CAE tools, for example, a schematic capture program may be used to generate a VHDL description for the design which can be used as an input to a simulation program.

• The language supports hierarchy, that is, a digital system can be modeled as a set of interconnected components; each component, in turn, can be modeled as a set of interconnected subcomponents.

• The language supportsflexible design methodologies: top-down, bottom-up, or mixed.

• The language is not technology-specific, but is capable of supporting technology-specific features. It can also support various hardware technologies, for example, you may define new logic types and new components, you may also specify technology-specific attributes. By being technology independent, the same behavior model can. be synthesized into different vendor libraries.

• It supports both synchronous and asynchronous timing models.

• Various digital modeling techniques such as finite-state machine descriptions, algorithmic descriptions, and boolean equations can be modeled using the language.

• The language is publicly available, human readable, machine readable, and above all, it is not proprietary.

• It is an IEEE and ANSI standard, and therefore, models described using this language are portable. The government also has a strong interest in maintaining this as a standard so that re-procurement and second-sourcing may become easier.

• The language supports three basic different description styles: structural, dataflow, and behavioral. A design may also be expressed in any combination of these three descriptive styles.

• It supports a wide range, of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. It does not, however, support modeling at or below the transistor level. It allows a design to be captured at a mixed level using a single coherent language.

• Arbitrarily large designs can be. modeled using the language and there are no limitations that are imposed by the language on the size of a design.

• The language has elements that make large scale design modeling easier, for example, components, functions, procedures, and packages.

• There is no need to learn a different language for simulation control. Test benches can be written using the same language to test other VHDL models.

• Nominal propagation delays, min-max delays, setup and hold timing, timing constraints, and spike detection can all be described very naturally in this language.

• The use of generics and attributes in the models facilitate back-annotation of static information such as timing or placement information.

• Generics and attributes are also useful in describing parameterized designs.

• A model can not only describe the functionality of a design, but can also contain information about the design itself 'in terms of user-defined attributes, for example, total area and speed.

• A common language can be used to describe library components from different vendors. Tools that understand VHDL models will have no difficulty in reading models from a variety of vendors since the language is a standard.

• Models written in this language can be verified by simulation since precise simulation semantics are defined for each language construct.

• Behavioral models that conform to a certain synthesis description style are capable of being synthesized to gate-level descriptions.

• The capability of defining new data types provides the power to describe and simulate a new design technique at a very high level of abstraction without any concern about the implementation details.

CIRCUIT ANALYSIS and FEEDBACK AMPLIFIER THEORY by Wai-Kai Chen

CIRCUIT ANALYSIS and FEEDBACK AMPLIFIER THEORY

Edited by
Wai-Kai Chen
A CRC title, part of the Taylor & Francis imprint, a member of the
Taylor & Francis Group, the academic division of T&F Informa plc.
Boca Raton London New York
University of Illinois
Chicago, U.S.A.

Download RAR File Link:

http://www.mediafire.com/?m30knmc9uttlcsh

GATE Papers for ECE from 2005 to 2012

GATE Exam Question papers for Electronics and Communication Engineering
  From year 2005 to 2012.

With the days to GATE 2013 is closing in I would like to share these Solved GATE Papers for ECE branch, which are solved as well. 
  TO ALL THE GATE EXAM 2013 aspirants BEST OF LUCK






DOWNLOAD LINKS For PDFS

GATE PAPER 2005:
http://www.mediafire.com/?zugjnilizmfwniq

GATE PAPER 2006:
http://www.mediafire.com/?ho1717dvm70q8gq

GATE PAPER 2007:
http://www.mediafire.com/?7r81oybw3ymzkqc

GATE PAPER 2008:
http://www.mediafire.com/?005jlhs4u65usd5

GATE PAPER 2009:
http://www.mediafire.com/?hja9ftgx0wsyhxl

GATE PAPER 2010:
http://www.mediafire.com/?z2vkdshc1sjxq40

GATE PAPER 2011:
http://www.mediafire.com/?5bc4d671ypzyt4e

GATE PAPER 2012:
http://www.mediafire.com/?b94mcc289k0i7x5

Facts About Digital Photography

History

• Eastman Kodak began experimenting with the use of Charge Couple Devices (CCD) as digital camera sensors in the 1970s. The first digital cameras appeared in the late 1980s, with the first consumer-ready cameras shipping in the 1990s.

How It Works

• Digital photography works similarly film photography, but an electronic sensor works in the place of film. The light from a subject enters the lens and is projected onto the digital sensor and recorded either in the camera's internal memory or to a removable device.

  Benefits

  • Digital photography provides instant results and cuts out the step of film development. The memory card size of the camera allows a photographer to take thousands of photos without stopping to change the film, allowing a better flow of action on a shoot.

  Disadvantages

  • Traditional film has a greater dynamic range, and so can capture more color and light than a camera sensor. As it involves the use of computers and specialized software for post-processing, digital photography can become very expensive.

  Potential

  • The rapid advances in digital photography mean that cameras have become smaller, lighter, and faster than ever; image quality from early digital cameras is easily trumped by even small cell phone cameras. With larger memory storage availability, photographers can store thousands of photos in virtually no space.

  
  

Mini/Minor Projects in Electronics and Communication Engineering

Given the rapid rise and fall of electronic communication formats, it is important to have a well-rounded view of electronic technology. With one-day mini projects, you can explore numerous technologies in a relatively short time. Split the class into teams to explore one avenue of technology each and present a group demonstration. This is a way to cover several technologies in a single session. Part of the joy of electrical engineering is in adapting seemingly obsolete technology to perform new applications.

FM Radio Projects

• The application of FM radio technology as widely varied short-range FM can be used in projects that transmit music and even electronic data. According to Electronics Project Designs project website, it is even possible to use the technology of FM radio to have students make their own walkie-talkies and portable home phone units. FM radio projects are ideally suited to students who enjoy the reallocation of older technology for modern applications as opposed to those more interested in what is cutting edge.

Optical Communication Projects

• Often we can look back into history for inspiration on how to approach the technical problems of today. One such project is to build an optical semaphore data transmission unit. Also known as an optical telegraph, these devices formed the basis upon which all modern documented equipment has evolved. According to the University of Calgary's historical report on optical telegraphs technology dates back to the 1600s, adapting it to modern uses such as computer data transmission or analog audio signals can be a nostalgic project. Lasers never cease to fascinate and captivate pupils, so why not have students set up a laser transmitter? Laser transmitters work in a fashion similar to that of optical semaphore transmission while being significantly more reliable and having a longer range.

Wireless Data Projects

• Wireless technologies, such as Bluetooth or the less popular Zigbee Standard, can be used to transmit data to and even control small devices at a short range. Applications of these technologies are nearly limitless, so directing students with specific objectives can help narrow it down for them. The design project website suggests giving students objectives such as the wireless synchronization of MP3 players or cameras; or for more mechanically minded students, perhaps even the control of a small robot.

  And Also from Image Processing Projects, Projects Based on VHDL and MATLAB, Project Based on Computer Network

VHDL Program on OR gate

   Every VHDL design description consists of at least one entity / architecture pair, or one entity with multiple architectures. The entity section of the HDL design is used to declare the I/O ports of the circuit, while the description code resides within architecture portion. Standardized design libraries are typically used and are included prior to the entity declaration. This is accomplished by including the code "library ieee;" and "use ieee.std_logic_1164.all;"

{CODE FOR OR gate }

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------

entity OR_ent is
port( x: in std_logic;
 y: in std_logic;
 F: out std_logic
);
end OR_ent;  

---------------------------------------

architecture OR_arch of OR_ent is
begin
    
    process(x, y)
    begin
        -- compare to truth table
        if ((x='0') and (y='0')) then
     F <= '0';
 else
     F <= '1';
 end if;
    end process;

end OR_arch;

architecture OR_beh of OR_ent is 
begin 

    F <= x or y; 

end OR_beh;

{SIMULATION}

Delay in VHDL without using a 'wait for' statement!

Introducing a delay in VHDL is pretty easy with a wait for statement. But it has the disadvantage that it is not synthesisable. Most of the practical designs, so require another way to introduce a delay.
   In this article I will use a counter and state machine to introduce the delay. We have an input signal, and we want to assign it to the output only after (say) 100 clock cycles. With this objective in my mind , first I have drawn a state machine.

There are two states in the state machine -  idle and  delay_c.
when the system is in idle state it waits for a valid input bit at the port data_in. whenever the data is valid, valid_data will go high. Upon receiving  a valid data, the system moves to delay_c state where a counter, c is incremented every clock cycle till it reaches the maximum delay value(Here it is 100). Once the max count is reached system goes back to idle state and the input data will be assigned to output data. This process goes on and on.

I have written the VHDL codes and testbench code for the above state machine. See the below simulated result to see how it works:

    The VHDL code is given below. It is well commented, so I wont be explaining it any further.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity delay is
port(   Clk : in std_logic;
        valid_data : in std_logic; -- goes high when the input is valid.
        data_in : in std_logic; -- the data input
        data_out : out std_logic --the delayed input data.
        );
end delay;

architecture Behaviora of delay is

signal c : integer := 0;
constant d : integer := 100; --number of clock cycles by which input should be delayed.
signal data_temp : std_logic := '0';
type state_type is (idle,delay_c); --defintion of state machine type
signal next_s : state_type; --declare the state machine signal.

begin

process(Clk)
begin
    if(rising_edge(Clk)) then
        case next_s is
            when idle =>
                if(valid_data= '1') then
                    next_s <= delay_c;
                    data_temp <= data_in; --register the input data.
                    c <= 1;
                end if;
            when delay_c =>
                if(c = d) then
                    c <= 1; --reset the count
                    data_out <= data_temp; --assign the output
                    next_s <= idle; --go back to idle state and wait for another valid data.
                else
                    c <= c + 1;
                end if;
            when others =>
                NULL;
        end case;
    end if;
end process;   

   
end Behaviora;

The following testbench code was used to test the code.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

   signal Clk : std_logic := '0';
   signal valid_data : std_logic := '0';
   signal data_in,data_out : std_logic := '0';
   constant Clk_period : time := 5 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: entity work.delay PORT MAP (
          Clk => Clk,
          valid_data => valid_data,
          data_in => data_in,
          data_out => data_out
        );

   -- Clock process definitions
   Clk_process :process
   begin
        Clk <= '0';
        wait for Clk_period/2;
        Clk <= '1';
        wait for Clk_period/2;
   end process;
   -- Stimulus process
   stim_proc: process
   begin       
      wait for 100 ns; 
        valid_data <= '1';
        data_in <= '1';
      wait;
   end process;

END;

The above design was successfully synthesized in Xilinx ISE software. Note that there are lot of different situations in which a delay can be introduced. But understanding the above concept well, will help you in most of the cases.

There is one limitation to this design. If the input value keep changing before the delay count is reached, then it will only take the first valid value. If you want a delay pipeline then you have to implement a FIFO whose size will depend on the amount of delay. In our case we will need  a FIFO size  of 100 bits. I will try to cover this in another article

Using real data types in VHDL

   Apart from the standard types like integer and std_logic_vector's VHDL also offer real data types. But a real data type has a big disadvantage. It is not synthesis-able. It can be used only for simulation purposes. This disadvantage limits its use to a large extend, but there are plenty of projects where we look only for simulation results.

  Before starting the coding part of a VHDL project,one has to decide whether the project to be implemented on a real FPGA or just a computer simulation is required. If it has to be ran on FPGA, then forget about the real package and use only synthesis-able data types like std_logic,integer etc... Otherwise you can reduce the time and complexity of your project by using real data types.

  The real data type is defined in the library called MATH_REAL. So you have to include the following line before the entity declaration in the code:
use ieee.math_real.all;

 The math_real package also offers some elementary mathematical functions for real data types. You can see the math_real.vhd file at the following address.

See the below code to get an idea on how to use these functions:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;

entity real_demo is
end real_demo;

architecture Behavioral of real_demo is

--signals declared with the REAL data type.
--MATH_PI is a constant defined in the math_real package.
signal X : real := -MATH_PI/3.0; --A real variable X, initialized to pi/3(60 degreee).
signal sign_result,ceil_result,floor_result,round_result,trunc_result : real := 0.0;
signal max,min,root,cube,power1,power2,exp_result : real := 0.0;
signal log_result,log2_result,log10_result,log_result2,sine,cosine,tangent : real := 0.0;
signal sin_inv,cos_inv,tan_inv,sin_hyp,cos_hyp,tan_hyp : real := 0.0;
signal inv_sin_hyp,inv_cos_hyp,inv_tan_hyp : real := 0.0;

begin

process
begin

sign_result <= SIGN(X);  --sign of X
ceil_result <= CEIL(X); --smallest integer value not less than X
floor_result <= FLOOR(X); --largest integer value not greater than X
round_result <= ROUND(X); --round to the nearest integer.
trunc_result <= TRUNC(X); --truncation.
max <= REALMAX(4.5,4.6); --return the maximum
min <= REALMIN(2.3,3.2); --return the minimum
root <= SQRT(4.0);  --square root
cube <= CBRT(64.0); --cube root
power1 <= 2**3.0; --power of an integer
power2 <= 3.0**3.0; --power of a real
exp_result <= EXP(1.0); --returns e**X.
log_result <= LOG(2.73); --natural logarithm
log2_result <= LOG2(16.0); --log to the base 2.
log10_result <= LOG10(100.0); --log to the base 10.
log_result2 <= LOG(27.0,3.0); --log to the given base.
sine <= SIN(X); --sine of the given angle(in rad)
cosine <= COS(X);--cosine of the given angle(in rad)
tangent <= TAN(X);--tangent of the given angle(in rad)
sin_inv <= ARCSIN(SIN(X)); --sine inverse.
cos_inv <= ARCCOS(COS(X)); --cosine inverse.
tan_inv <= ARCTAN(TAN(X)); --tangent inverse.
sin_hyp <= SINH(X); --Hyperbolic sine
cos_hyp <= COSH(X); --Hyperbolic cosine.
tan_hyp <= TANH(X); --Hyperbolic tangent.
inv_sin_hyp <= ARCSINH(SINH(X)); --Inverse hyperbolic sine.
inv_cos_hyp <= ARCCOSH(COSH(X)); --Inverse hyperbolic cosine.
inv_tan_hyp <= ARCTANH(TANH(X)); --Inverse hyperbolic tangent.
wait;

end process;    

end Behavioral;