VHDL Tutorial :Basic Terminology

Basic Terminology

   VHDL is a hardware description language that can be used to model a digital system. The digital system can be as simple as a logic gate or as complex as a complete electronic system. A hardware abstraction of this digital system is called an entity in this text. An entity X, when used in another entity Y, becomes a component for the entity Y. Therefore, a component is also an entity, depending on the level at which you are trying to model.

   To describe an entity, VHDL provides five different types of primary constructs, called" design units.

They are

1.  Entity declaration

2.  Architecture body

3.  Configuration declaration

4.  Package declaration

5.  Package body

   An entity is modeled using an entity declaration and at least one architecture body. The entity declaration describes the external view of the entity, for example, the input and output signal names. The architecture body contains the internal description of the entity, for example, as a set of interconnected components that represents the structure of the entity, or as a set of concurrent or sequential statements that represents the behavior of the entity. Each style of representation can be specified in a different architecture body or mixed within a single architecture body Figure 2.1 shows an entity and its model.

Figure 2.1 An entity and its model

   A configuration declaration is used to create a configuration for an entity. It specifies the binding of one architecture body from the many architecture bodies that may be associated with the entity. It may also specify the bindings of components used in the selected architecture body to other entities. An entity may have any number of different configurations.

A package declaration encapsulates a set of related declarations such as type declarations, subtype declarations, and subprogram declarations that can be shared across two or more design units. A package body contains the definitions of subprograms declared in a package declaration.

Figure 2.2 shows three entities called El, E2, and E3. Entity El has three architecture bodies, EI_AI, EI_A2, and EI_A3. Architecture body EI_AI is a purely behavioral model without any hierarchy. Architecture body EI_A2 uses a component called BX, while architecture body EI_A3 uses a component called CX. Entity E2 has two architecture bodies, E2_AI and E2_A2, and architecture body E2_AI uses a component called MI. Entity E3 has three architecture bodies, E3_AI, E3_A2, and E3_A3. Notice that each entity has a single entity declaration but more than one architecture body.

The dashed lines represent the binding that may be specified in a configuration for entity El. There are two types of binding shown: binding of an architecture body to its entity and the binding of components used in the architecture body with other entities. For example, architecture body, EI_A3, is bound to entity El, while architecture body, E2_AI, is bound to entity E2. Component MI in architecture body, E2_AI, is bound to entity E3. Component CX in the architecture body, EI_A3, is bound to entity E2. However, one may choose a different configuration for entity El with the following bindings:

•   Architecture EI_A2 is bound to its entity El

•  Component BX to entity E3

•  Architecture E3_AI is bound to its entity E3

Figure 2.2 A configuration for entity El

   Once an entity has been modeled, it needs to be validated by a VHDL system. A typical VHDL system consists of an analyzer and a simulator. The analyzer reads in one or more design units contained in a single file and compiles them into a design library after validating the syntax and performing some static semantic checks. The design library is a place in the host environment (that is, the environment that supports the VHDL system) where compiled design units are stored.

   The simulator simulates an entity, represented by an entity-architecture pair or by a configuration, by reading in its compiled description from the design library and then performing the following steps:

1. Elaboration

2. Initialization

3. Simulation

   A note on the language syntax. The language is casc-iriSRissitive, that is, lower-case and upper-case characters are treated alike. For example, CARRY, CarrY, or CarrY, all refer to the same name. The language is also free -format, very much like in Ada and Pascal programming languages. Comments are specified in the language by preceding the text with two consecutive dashes (-). All text between the two dashes and the end of that line is treated as a comment.