VHDL Tutorial : Mixed Style of Modeling

4. Mixed Style of Modeling

1.FULL ADDER

   It is possible to mix the three modeling styles that we have seen so far in a single architecture body. That is, within an architecture body, we could use component instantiation statements (that represent structure), concurrent signal assignment statements (that represent dataflow), and process statements (that represent behavior). Here is an example of a mixed style model for a one-bit full-adder shown in Fig. 2.7.

entity FULL_ADDER is

port (A, B, CIN: in BIT; SUM, COUT: out BIT);

end FULL_ADDER;

architecture FA_MIXED of FULL_ADDER is

component XOR2

port (A, B: in BIT; Z: out BIT);

end component;

signal S1: BIT;

begin

X1: XOR2 port map (A, B, S1 ); - structure.

process (A, B, CIN) - behavior.

variable T1, T2, T3: BIT;

begin

T1 :=A and B;

T2 := B and CIN;

T3:=A and CIN;

COUT <= T1 or T2 or T3;

end process;

SUM <= S1 xor CIN; - dataflow.

end FA_M!XED;

Figure 2.7 A 1-bit full-adder

   The full-adder is represented using one component instantiation statement, one process statement and one concurrent signal assignment statement. All of these statements are concurrent statements, and therefore, their order of appearance within the architecture body is not important. Note that a process statement itself is a concurrent statement; however, statements within a process statement are always executed sequentially. SI is a signal locally declared within the architecture body and is used to pass the value from the output of the component XI to the expression for signal SUM.