VHDL Tutorial : Behavioral Style of Modeling

3. Behavioral Style of Modeling

1. DECODER2x4

In contrast to the styles of modeling described earlier, the behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order. This set of sequential statements, that are specified inside a process statement, do not explicitly specify the structure of the entity but merely specifies its functionality. A process statement is a concurrent statement that can appear within an architecture body. For example, consider the following behavioral model for the DECODER2x4 entity.

architecture DEC_SEQUENTIAL of DECODER2x4 is 

begin 

process (A, B, ENABLE)

variable ABAR, BBAR: BIT; 

begin

ABAR := not A;                                             - statement 1 

BBAR := not B;                                              - statement 2 

if (ENABLE = '1') then                                    -statements 

Z(3) <= not (A and B):                                    - statement 4 

Z(0) <= not (ABAR and BBAR);                    -statement 5 

Z(2) <= not (A and BBAR);                            - statement 6 

Z(1 ) <= not (ABAR and B);                           - statement 7 

else

Z<= "1111";                                                   -statement 8

end if; 

end process; 

end;

 Figure 2.4 A 2-to-4 decoder circuit

   A process statement, too, has a declarative part (between the keywords process and begin), and a statement part (between the keywords begin and end process). The statements appearing within the statement part are sequential statements and are executed sequentially. The list of signals specified within the parenthesis after the keyword process constitutes a sensitivity list and the process statement is invoked whenever there is an event on any signal in this list. In the previous example, when an event occurs on signals A, B, or ENABLE, the statements appearing within the process statement are executed sequentially.

The variable declaration (starts with the keyword variable) declares two variables called ABAR and BBAR. A variable is different from a signal in that it is always assigned a value instantaneously and the assignment operator used is the := compound symbol; contrast this with a signal that is assigned a value always after a certain delay (user-specified or the default delta delay), and the assignment operator used to assign a value to a signal is the <= compound symbol. Also, variables can only be declared within a process and their scope is limited to that process (variables can also be declared in subprograms). Note, however, that signals cannot be declared within a process.

   Signal assignment statements appearing within a process are called sequential signal assignment statements. Sequential signal assignment statements, including variable assignment statements, are executed sequentially independent of whether an event occurs on any signals in its right-hand-side expression or not; contrast this with the execution of concurrent signal assignment statements in the dataflow modeling style. In the previous architecture body, if an event occurs on any signal. A, B, or ENABLE, statement I which is a variable assignment statement, is executed, then statement 2 is executed, and so on. Execution of the third statement, an if statement, causes control to jump to the appropriate branch based on the value of the signal, ENABLE. If the value of ENABLE is 1', the next four signal assignment statements, 4 through 7, are executed independent of whether A, B, ABAR, or BBAR changed values, and the target signals are scheduled to get their respective values after delta delay. If ENABLE has a value '0', a value of 'V is assigned to each of the elements of the output array, Z. When execution reaches the end of the process, the process suspends itself, and waits for another event to occur on a signal in its sensitivity list.

2.CLOCK

   It is possible to use case or loop statements within a process. The semantics and structure of these statements are very similar to those in other high-level programming languages like C or Pascal. An explicit wait statement can also be used to suspend a process. It can be used to wait for a certain amount of time or to wait until a certain condition becomes true, or to wait until an event occurs on one or more signals. Here is an example of a process statement that generates a clock with a different on-off period. Figure 2.6 shows the generated waveform.

process

begin

CLK <= '0' ;

wait for 20 ns;

CLK <= '1' ;

wait for 12 ns;

end process;

Figure 2.6 A clock waveform with varying on-off period

This process does not have a sensitivity list since explicit wait statements are present inside the process. It is important to remember that a process never terminates. It is always either being executed or in a suspended state. All processes are executed once during the initialization phase of simulation until they get suspended. Therefore, a process with no sensitivity list and with no explicit wait statements will never suspend itself.

3. D FLIP-FLOP

A signal can represent not only a wire but also a place holder for a value, that is, it can be used to model a flip-flop. Here is such an example. Port signal Q models a level-sensitive flip-flop.

entity LS_DFF is

port (Q: out BIT; D, CLK: in BIT):

end LS_DFF;

architecture LS_DFF_BEH of LS_DFF is

begin

process (D, CLK)

begin

if (CLK = '1') then

Q <= D;

end if;

end process;

end LS_DFF_BEH;