VHDL Tutorials: Program for 4x1 Multiplexer

   The Program for a 4x1 Multipexer using CASE statement is :

use IEEE.std_logic_1164.all;


-- this is the entity

entity MUX is
port (A, B, C, D: in BIT; CTRL: in BIT_VECTOR(0 to 1);
Z: out BIT);
end MUX;

-- this is the architecture
architecture MUX_BEHAVIOR of MUX is
constant MUX_DELAY: TIME := 10 ns;
begin
PMUX: process (A, B, C, D, CTRL)
variable TEMP: BIT;
begin
case CTRL is
when "00" => TEMP := A:
when "01" => TEMP := B;
when "10" => TEMP := C;
when "11" => TEMP := D;
end case;
Z <= TEMP after MUX_DELAY;
end process PMUX;
end MUX_BEHAVIOR;

  The simulated testbench waveform is shown below:

 The code was synthesized using XILINX ISE XST . The RTL schematic of the design is shown below.