VHDL Tutorial : Entity Declaration

Entity Declaration

   The entity' declaration specifies the name of the entity being modeled and lists the set of interface ports. Ports are signals through which the entity communicates with the other models in its external environment.

Figure 2.3 A half-adder circuit

Here is an example of an entity declaration for the half-adder circuit shown in Fig. 2.3.

entity HALF_ADDER is

port (A, B: in BIT; SUM, CARRY: out BIT); end HALF_ADDER;

-- This is a comment line.

   The entity, called HALF_ADDER, has two input ports, A and B (the mode in specifies input port), and two output ports, SUM and CARRY (the mode out specifies output port). BIT is a predefined type of the language; it is an enumeration type containing the character literals '0' and '1'. The port types for this entity have been specified to be of type BIT, which means that the ports can take the values, '0' or '1'.

The following is another example of an entity declaration for a 2-to-4 decoder circuit shown in Fig. 2.4.

entity DECODER2x4 is

port (A, B, ENABLE: in SIT: Z: out BIT_VECTOR(0 to 3)); end DECODER2x4;

 Figure 2.4 A 2-to-4 decoder circuit

 This entity, called DECODER2x4, has three input ports and four output ports. BIT_VECTOR is a predefined unconstrained array type of BIT. An unconstrained array type is a type in which the size of the array is not specified. The range "0 to 3" for port Z specifies the array size.

   From the last two examples of entity declarations, we see that the entity declaration does not specify anything about the internals of the entity. It only specifies the name of the entity and the interface ports.