VHDL Tutorial : Structural Style of Modeling

Architecture Body

   The internal details of an entity are specified by an architecture body using any of the following modeling styles:

1. As a set of interconnected components (to represent structure),

2. As a set of concurrent assignment statements (to represent dataflow),

3. As a set of sequential assignment statements (to represent be-hav.ior),

4. Any combination of the above three.

1. Structural Style of Modeling

1.HALF ADDER

   In the structural style of modeling, an entity is described as a set of interconnected components. Such a model for the HALF_ADDER entity, shown in Fig. 2.3, is described in an architecture body as shown below.

architecture HA_STRUCTURE of HALF_ADDER is

component XOR2

port (X, Y: in BIT; Z: out BIT);

end component;

component AND2

port (L, M: in BIT; N: out BIT);

end component;

begin

X1: XOR2 port map (A, B, SUM);

A1: AND2 port map (A, B, CARRY);

end HA_STRUCTURE;

Figure 2.3 A half-adder circuit

The name of the architecture body is HA_STRUCTURE. The entity declaration for HALF_ADDER (presented in the previous section) specifies the interface ports for this architecture body. The architecture body is composed of two parts: the declarative part (before the keyword begin) and the statement part (after the keyword begin). Two component declarations are present in the declarative part of the architecture body. These declarations specify the interface of components that are used in the architecture body. The components XOR2 and AND2 may either be predefined components in a library, or if they do not exist, they may later be bound to other components in a library.

The declared components are instantiated in the statement part of the architecture body using component instantiation statements. XI and A1 are the component labels for these component instantiations. The first component instantiation statement, labeled XI, shows that signals A and B (the input ports of the HALF_ADDER), are connected to the X and Y input ports of a XOR2 component, while output port Z of this component is connected to output port SUM of the HALF_ADDER entity.

Similarly, in the second component instantiation statement, signals A and B are connected to ports L and M of the AND2 component, while port N is connected to the CARRY port of the HALF_ADDER. Note that in this case, the signals in the port map of a component instantiation and the port signals in the component declaration are associated by position (called positional association). The structural representation for the HALF_ADDER does not say anything about its functionality. Separate entity models would be described for the components XOR2 and AND2, each having its own entity declaration and architecture body.

2.DECODER2x4

   A structural representation for the DECODER2x4 entity, shown in Fig. 2.4, is shown next.

architecture DEC_STR of DECODER2x4 is

component INV

port (A: in BIT; Z: out BIT);

end component;

component NAND3

port (A, B, C: in BIT; Z: out BIT);

end component;

signal ABAR, BBAR: BIT;

begin

I0: INV port map (A, ABAR);

I1: INV port map (B, BBAR);

N0: NAND3 port map (ABAR, BBAR, ENABLE, Z(0));

N1: NAND3 port map (ABAR, B, ENABLE, Z(1));

N2: NAND3 port map (A, BBAR, ENABLE, Z(2));

N3: NAND3 port map (A, B, ENABLE, Z(3));

end DEC_STR;

 Figure 2.4 A 2-to-4 decoder circuit

   In this example, the name of the architecture body is DEC_STR, and it is associated with the entity declaration with the name DECODER2x4; therefore, it inherits the list of interface ports from that entity declaration. In addition to the two component declarations (for INV and NAND3), the architecture body contains a signal declaration that declares two signals, ABAR and BBAR, of type BIT. These signals, that represent wires, are used to connect the various components that form the decoder. The scope of these signals is restricted to the architecture body, and therefore, these signals are not visible outside the architecture body. Contrast these signals with the ports of an entity declaration that are available for use within any architecture body associated with the entity declaration.

A component instantiation statement is a concurrent statement, as defined by the language. Therefore, the order of these statements is not important. The structural style of modeling describes only an interconnection of components (viewed as black boxes) without implying any behavior of the components themselves, nor of the entity that they collectively represent. In the architecture body DEC_STR, the signals A, B, and ENABLE, used in the component instantiation statements are the input ports declared in the DECODER2x4 entity declaration. For example, in the component instantiation labeled N3, port A is connected to input A of component NAND3, port B is connected to input port B of component NAND3, port ENABLE is connected to input port C, and the output port Z of component NAND3 is connected to port Z(3) of the DECODER2x4 entity. Again positional association is used to map signals in a port map of a component instantiation with the ports of a component specified in its declaration. The behavior of the components NAND3 and INV are not apparent, nor is the behavior of the decoder entity that the structural model represents.