AIEEE 2011 Cut Off For IIIT ALLAHABAD

...[Readmore]

MANIT BHOPAL Branchwise AIEEE 2011 Cut off

...[Readmore]

AIEEE Counselling 2012

AIEEE Counselling 2012 Dates Seat Allotment Procedure Registration AIEEE Counselling 2012 - AIEEE Counselling 2012 is going to held in the month of June-July and August. The candidate may register for appearing in the Counselling of AIEEE on 16 June to 25 June. the various tentative dates for the seats allotment Procedure Registration is all given below.The AIEEE Counselling first round will going to start in the last week of the...[Readmore]

Using real data types in VHDL

Apart from the standard types like integer and std_logic_vector's VHDL also offer real data types. But a real data type has a big disadvantage. It is not synthesis-able. It can be used only for simulation purposes. This disadvantage limits its use to a large extend, but there are plenty of projects where we look only for simulation results.  Before starting the coding part of a VHDL project,one has to decide whether the project...[Readmore]

Why the library "numeric_std" is preferred over "std_logic_arith" and others?

This article is based on an email conversion I had with one VHDL expert.If you browse through some forums about VHDL then you may see some suggestions such as , use "numeric_std" library instead of "std_logic_arith" and "std_logic_unsigned".I had this doubt before and here is what he(unfortunately i don't know his name) told me:     std_logic_arith, etc. were packages written by Synopsis and included in their tools'...[Readmore]

Usage of Packages and functions

Packages are the only language mechanism to share objects among different design units. Usually, they are designed to provide standard solutions for specific problems, e.g. data types and corresponding subprograms like type conversion functions for different data types, procedures and functions for signal processing purposes, etc.A package is declared in the following format :  package package_name is     -- Declaration...[Readmore]

How to write a testbench?

Once you finish writing code for your design,you need to test whether it is working or not.One method of testing your design is by writing a testbench code.Without going much into the details I will give you an example.     Below is a program for a basic 4 bit counter with reset input : library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity test isport (clk : in std_logic; ...[Readmore]

VHDL Programs on Simple 4 : 1 multiplexer using case statements

Here is the code for 4 : 1 MUX using case statements.The module contains 4 single bit input lines and one 2 bit select input.The output is a single bit line. library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity multiplexer4_1 isport (      i0 : in std_logic;      i1 : in std_logic;      i2 : in std_logic;      i3 : in std_logic;  ...[Readmore]

Vhdl Program 3 bit Magnitude Comparator using logic gates

 I have been getting lot of requests asking for VHDL code for digital comparators. In this post I have shared a 3 bit comparator which is designed using basic logic gates such as XNOR, OR, AND etc. The code was tested using  a testbench code which tested the design for all the 81 combinations of inputs.See the code below: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity comparator isport( a,b : in unsigned(2 downto 0);  --3...[Readmore]