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AIEEE Counselling 2012

AIEEE Counselling 2012 Dates Seat Allotment Procedure Registration

AIEEE Counselling 2012 - AIEEE Counselling 2012 is going to held in the month of June-July and August. The candidate may register for appearing in the Counselling of AIEEE on 16 June to 25 June. the various tentative dates for the seats allotment Procedure Registration is all given below.

The AIEEE Counselling first round will going to start in the last week of the June. The candidates can know more about the AIEEE Counselling 2012 as follows:

AIEEE Counselling 2012 - Details

Important Dates of Seat Allotment:

• Online Registration - June16 - 25 
• First round - June 27
• Reporting RC against first round - June 28 - July 2
• Second Round - July 5
• Reporting RC against 2nd round - July 6 - 10
• Third round - July 12
• Reporting RC against third round - July 13 - 16
• Admission - July 17 - 22
• Modification Online - July 17 -22
• Fourth Round - July 25
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• INTERNAL SLIDING (separately institute) - August 1
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• Fresher registration for Spot round, filling up of choices and choice locking at RC - Aug 3 - 6
• Spot round seat allotment and automatic admissions to CFI - Aug 8
• Reporting to allotted institute for the admission against the spot round allotment - Aug 9 -12
• Reporting to class in Centrally Funded Institutes (CSIs) - Aug 9 -10

Using real data types in VHDL

Apart from the standard types like integer and std_logic_vector's VHDL also offer real data types. But a real data type has a big disadvantage. It is not synthesis-able. It can be used only for simulation purposes. This disadvantage limits its use to a large extend, but there are plenty of projects where we look only for simulation results.

  Before starting the coding part of a VHDL project,one has to decide whether the project to be implemented on a real FPGA or just a computer simulation is required. If it has to be ran on FPGA, then forget about the real package and use only synthesis-able data types like std_logic,integer etc... Otherwise you can reduce the time and complexity of your project by using real data types.

The real data type is defined in the library called MATH_REAL. So you have to include the following line before the entity declaration in the code:
use ieee.math_real.all;

The math_real package also offers some elementary mathematical functions for real data types. You can see the math_real.vhd file at thefollowing address.

See the below code to get an idea on how to use these functions:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;

entity real_demo is
end real_demo;

architecture Behavioral of real_demo is

--signals declared with the REAL data type.
--MATH_PI is a constant defined in the math_real package.
signal X : real := -MATH_PI/3.0; --A real variable X, initialized to pi/3(60 degreee).
signal sign_result,ceil_result,floor_result,round_result,trunc_result : real := 0.0;
signal max,min,root,cube,power1,power2,exp_result : real := 0.0;
signal log_result,log2_result,log10_result,log_result2,sine,cosine,tangent : real := 0.0;
signal sin_inv,cos_inv,tan_inv,sin_hyp,cos_hyp,tan_hyp : real := 0.0;
signal inv_sin_hyp,inv_cos_hyp,inv_tan_hyp : real := 0.0;

begin

process
begin

sign_result <= SIGN(X);  --sign of X
ceil_result <= CEIL(X); --smallest integer value not less than X
floor_result <= FLOOR(X); --largest integer value not greater than X
round_result <= ROUND(X); --round to the nearest integer.
trunc_result <= TRUNC(X); --truncation.
max <= REALMAX(4.5,4.6); --return the maximum
min <= REALMIN(2.3,3.2); --return the minimum
root <= SQRT(4.0);  --square root
cube <= CBRT(64.0); --cube root
power1 <= 2**3.0; --power of an integer
power2 <= 3.0**3.0; --power of a real
exp_result <= EXP(1.0); --returns e**X.
log_result <= LOG(2.73); --natural logarithm
log2_result <= LOG2(16.0); --log to the base 2.
log10_result <= LOG10(100.0); --log to the base 10.
log_result2 <= LOG(27.0,3.0); --log to the given base.
sine <= SIN(X); --sine of the given angle(in rad)
cosine <= COS(X);--cosine of the given angle(in rad)
tangent <= TAN(X);--tangent of the given angle(in rad)
sin_inv <= ARCSIN(SIN(X)); --sine inverse.
cos_inv <= ARCCOS(COS(X)); --cosine inverse.
tan_inv <= ARCTAN(TAN(X)); --tangent inverse.
sin_hyp <= SINH(X); --Hyperbolic sine
cos_hyp <= COSH(X); --Hyperbolic cosine.
tan_hyp <= TANH(X); --Hyperbolic tangent.
inv_sin_hyp <= ARCSINH(SINH(X)); --Inverse hyperbolic sine.
inv_cos_hyp <= ARCCOSH(COSH(X)); --Inverse hyperbolic cosine.
inv_tan_hyp <= ARCTANH(TANH(X)); --Inverse hyperbolic tangent.
wait;

end process;   

end Behavioral;

Almost all the functions available in the real package are shown above and comments are provided on what they are used for. For your reference I have attached the simulation result below:

As you can see its a pretty useful library. Dont forget to use it if you have a simulation project in VHDL. Contact me for any kind of help. I always use this package when I need to convert a matlab code to corresponding VHDL(for just simulation). Using this package, helps me to write the vhdl code like a pseudo code. 

Why the library "numeric_std" is preferred over "std_logic_arith" and others?

This article is based on an email conversion I had with one VHDL expert.If you browse through some forums about VHDL then you may see some suggestions such as , use "numeric_std" library instead of "std_logic_arith" and "std_logic_unsigned".I had this doubt before and here is what he(unfortunately i don't know his name) told me:

    std_logic_arith, etc. were packages written by Synopsis and included in their tools' version of the ieee library, without the approval of the ieee standardization body. The LRM (Language reference manual) reserves the ieee library for officially balloted and approved packages for the vhdl language.However, since the whole world started using synopsys first, and everyone had started writing code dependent upon std_logic_arith being in ieee, Synopsys refused to take it out of their implementation. And since other tools were usually forced to work seamlessly with code that worked with Synopsys, they followed suit. However, different vendors implemented the package slightly differently, with some problems in compatibility. Since there is no standard governing it, it is subject to change at any time. 

     So, the IEEE decided to write and approve a standard package for numerical operations on SL(std_logic) and BIT based vectors. Those packages are called numeric_std and numeric_bit. These are ieee standard packages, located in the official version of the ieee library, and their behavior is governed by the standard, so compatibility is assured.

  

    Numeric_std does not attempt to imply a numerical interpretation on SLV(std_logic_vector) , but rather defines related types UNSIGNED and SIGNED which have both numerical and bitwise interpretations (i.e.AND and OR are also defined for them). This avoids any confusion when needing to use both signed and unsigned arithmetic in the same body (std_logic_arith simply assumes all arithmetic is unsigned). Numeric_std defines arithmetic operations between various combinations of signed, unsigned and integer operands. In all cases(?) the size of the result is the same as the largest signed/unsigned operand. Over/underflows are truncated (rolled over). 

     The latest version of the vhdl standard does include a package similar in function to std_logic_arith, etc., named numeric_std_unsigned, which does define unsigned arithmetic on std_logic_vector operands. Unfortunately, I know of no tools that support it yet.

     Generally, if you can, create your entity interfaces using unsigned or signed (or even integer) if they are uniformly numerically interpreted. (i.e. a generic memory device may be able to store any kind of binary data, so SLV may make more sense there, but a digital filter has a specific definition of its input data in mind, and that can be coded by using the appropriate type on the port). Using the appropriate types on the ports makes it much easier to avoid conversions within the body.

For example, if you used an SLV input port, and you need to add one to it and output that on an SLV output port, you must convert it twice: 

output <= std_logic_vector(unsigned(input) + 1); 

This converts the SLV input to unsigned (so that + is defined for it), adds (integer) one to it (the result is unsigned too), then converts the result back to SLV for the output port.It would have been much easier if input and output had been declared unsigned (or signed) in the first place:  

output <= input + 1;

    At the same time you shouldn't get the idea that "don't use SLV at all".Some places SLV is better than UNSIGNED or SIGNED data type.For example, an ALU (Arithmetic and Logic Unit) that accepts signed or unsigned data (depending on the operation control) may always have a numeric interpretation of the data on its ports, but since we do not have a generic numeric signed and unsigned representation, SLV would still be appropriate for those ports.Other examples,where SLV is  a better option are any collection of bits that does not have a numeric meaning such as a vector of enable bits, etc...

 

Note :- In the earlier codes I have heavily dependent on SLV.But in the recent posts I have started using SIGNED and UNSIGNED data types more frequently.  

Usage of Packages and functions

Packages are the only language mechanism to share objects among different design units. Usually, they are designed to provide standard solutions for specific problems, e.g. data types and corresponding subprograms like type conversion functions for different data types, procedures and functions for signal processing purposes, etc.A package is declared in the following format :

 package package_name is
     -- Declaration of
          -- types and subtypes
          -- subprograms
          -- constants, signals etc.
 end package_name;


package body package_name is
     -- Definition of previously declared
        -- constants
        -- subprograms
     -- Declaration/definition of additional
        -- types and subtypes
        -- subprograms
        -- constants, signals and shared variables
end package_name;

--An example for a module using package..
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--note this line.The package is compiled to this directory by default.
--so don't forget to include this directory. 
library work;
--this line also is must.This includes the particular package into your program.
use work.test_pkg.all;

entity test is
port (clk : in std_logic;
      a1 : in t1;
      b1 : in t1;
      c1: out t1
    );
end test;

architecture Behavioral of test is
begin
process(clk)
begin
if(clk'event and clk='1') then
c1<=add(a1,b1);   --for doing xor operation at every positive edge of clock cycle.
end if;
end process;
end Behavioral;



--Package declaration for the above program
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

package test_pkg is
type t1 is  --a data type(totally 32 bits contains 3 different fields)
    record
        a :std_logic_vector(11 downto 0);
        b :std_logic_vector(15 downto 0);
        c :std_logic_vector(3 downto 0);
    end record;

 --function declaration.
function add (a2 : t1; b2: t1) return t1;
end test_pkg;   --end of package.

package body test_pkg is  --start of package body
--definition of function
function  add (a2 : t1; b2: t1) return t1 is
variable sum : t1;
begin -- Just name the fields in order...
sum.a:=a2.a xoR b2.a;
sum.b:=a2.b xoR b2.b;
sum.c:=a2.c xoR b2.c;
return sum;
end add;
--end function
end test_pkg;  --end of the package body

      The above program calculates the 'xor' of a 32 bit data type containing 3 fields.If you don't use a function then it is not possible to directly apply the 'xor' function to different data types like 't1'. If you want to use this function at many places in your program then it is advisable to use packages(or functions).
      Another advantage of packages is that by just editing the data types or functions in the package body alone you can do some minor modifications in your design.Otherwise you may need to change your code at lot of places.

How to write a testbench?

Once you finish writing code for your design,you need to test whether it is working or not.One method of testing your design is by writing a testbench code.Without going much into the details I will give you an example.
     Below is a program for a basic 4 bit counter with reset input :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
port (clk : in std_logic;
      count : out std_logic_vector(3 downto 0);
      reset :in std_logic
     );
end test;

architecture Behavioral of test is
signal c : std_logic_vector(3 downto 0) :=(others => '0');  --initializing count to zero.
begin
count <= c;
process(clk,reset)
begin
if(clk'event and clk='1') then
-- when count reaches its maximum(that is 15) reset it to 0
if(c = "1111") then
c <="0000";
end if;
c <= c+'1';  --increment count at every positive edge of clk.
end if;
if(reset='1') then  --when reset equal to '1' make count equal to 0.
c <=(others => '0');  -- c ="0000"
end if;
end process;

end Behavioral;

Now I will give a sample test bench for the above code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_tb IS
END test_tb;

ARCHITECTURE behavior OF test_tb IS
   -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT test  --'test' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such. 
    PORT(
         clk : IN  std_logic;
         count : OUT  std_logic_vector(3 downto 0);
         reset : IN  std_logic
        );
    END COMPONENT;
   --declare inputs and initialize them
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   --declare outputs and initialize them
   signal count : std_logic_vector(3 downto 0);
   -- Clock period definitions
   constant clk_period : time := 1 ns;
BEGIN
    -- Instantiate the Unit Under Test (UUT)
   uut: test PORT MAP (
         clk => clk,
          count => count,
          reset => reset
        );      

   -- Clock process definitions( clock with 50% duty cycle is generated here.
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        clk <= '1';
        wait for clk_period/2;  --for next 0.5 ns signal is '1'.
   end process;
   -- Stimulus process
  stim_proc: process
   begin        
        wait for 7 ns;
        reset <='1';
        wait for 3 ns;
        reset <='0';
        wait for 17 ns;
        reset <= '1';
        wait for 1 ns;
        reset <= '0';
        wait;
  end process;

END;

I think the code is self explanatory.I have given comments so that you can easily follow it. Now add these programs to your project and compile them.Once compilation is over click on "simulate Behavioral Model".You will get the following waveform.

    As you can see,whenever my reset=1,count value is zero.Otherwise count increments upto 15 and then get reset to zero.
Now a little more explanation about the test bench code:
    1) wait for 7 ns; means the simulator doesn't do anything for 7 nano second.If you want 7 ms delay instead of  7 ns then just replace ns with ms.
    2)The process named "clock_process" is  must in any test bench because it is used to generate clock for your module.Any main module always work with this clock.The period and duty cycle of the clock can be changed by editing this process.
    3)Your main module has to be given as a component in your test bench program inside "architecture".
    4)Your module has to be instantiated after the 'begin' statement.

VHDL Programs on Simple 4 : 1 multiplexer using case statements

Here is the code for 4 : 1 MUX using case statements.The module contains 4 single bit input lines and one 2 bit select input.The output is a single bit line.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplexer4_1 is
port (
      i0 : in std_logic;
      i1 : in std_logic;
      i2 : in std_logic;
      i3 : in std_logic;
     sel : in std_logic_vector(1 downto 0);
     bitout : out std_logic
     );
end multiplexer4_1;

architecture Behavioral of multiplexer4_1 is
begin

process(i0,i1,i2,i3,sel)
begin
case sel is
  when "00" => bitout <= i0;
  when "01" => bitout <= i1;
  when "10" => bitout <= i2;
  when others => bitout <= i3;
end case;
end process;

end Behavioral;

The testbench code used for testing the code is given below:

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS
          SIGNAL i0,i1,i2,i3,bitout :  std_logic:='0';
          SIGNAL sel :  std_logic_vector(1 downto 0):="00";
  BEGIN
    UUT : entity work.multiplexer4_1 port map(i0,i1,i2,i3,sel,bitout);

     tb : PROCESS
     BEGIN
            i0<='1';
            i1<='0';
            i2<='1';
            i3<='0';
            sel <="00";
            wait for 2 ns;
            sel <="01";
            wait for 2 ns;
            sel <="10";
             wait for 2 ns;
             sel <="11";
              wait for 2 ns;
            --more input combinations can be given here.
     END PROCESS tb;

  END;

     The simulated testbench waveform is shown below:

  The code was synthesized using XILINX ISE XST . The RTL schematic of the design is shown below.

Note :- Use RTL Viewer to get a closer look on how your design is implemented in hardware.

Vhdl Program 3 bit Magnitude Comparator using logic gates

 I have been getting lot of requests asking for VHDL code for digital comparators. In this post I have shared a 3 bit comparator which is designed using basic logic gates such as XNOR, OR, AND etc. The code was tested using  a testbench code which tested the design for all the 81 combinations of inputs.

See the code below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity comparator is
port( a,b : in unsigned(2 downto 0);  --3 bit numbers to be compared
        a_eq_b : out std_logic;  --a equals b
        a_le_b : out std_logic;  --a less than b
        a_gt_b : out std_logic   --a greater than b
      );    
end comparator;

architecture gate_level of comparator is

signal temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8,temp9 : std_logic := '0';

BEGIN

temp1 <= not(a(2) xor b(2));  --XNOR gate with 2 inputs.
temp2 <= not(a(1) xor b(1));  --XNOR gate with 2 inputs.
temp3 <= not(a(0) xor b(0));  --XNOR gate with 2 inputs.
temp4 <= (not a(2)) and b(2);
temp5 <= (not a(1)) and b(1);
temp6 <= (not a(0)) and b(0);
temp7 <= a(2) and (not b(2));
temp8 <= a(1) and (not b(1));
temp9 <= a(0) and (not b(0));

a_eq_b <= temp1 and temp2 and temp3;  -- for a equals b.
a_le_b <= temp4 or (temp1 and temp5) or (temp1 and temp2 and temp6); --for a less than b
a_gt_b <= temp7 or (temp1 and temp8) or (temp1 and temp2 and temp9); --for a greater than b

end gate_level;

The testbench code for testing the design is given below:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS 
   --Inputs
   signal a : unsigned(2 downto 0) := (others => '0');
   signal b : unsigned(2 downto 0) := (others => '0');
    --Outputs
   signal a_eq_b : std_logic;
   signal a_le_b : std_logic;
   signal a_gt_b : std_logic;

    signal i,j : integer;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: entity work.comparator PORT MAP (
          a => a,
          b => b,
          a_eq_b => a_eq_b,
          a_le_b => a_le_b,
          a_gt_b => a_gt_b
        );

   -- Stimulus process
   stim_proc: process
   begin        
        for i in 0 to 8 loop
            for j in 0 to 8 loop
                a <= to_unsigned(i,3); --integer to unsigned type conversion
                b <= to_unsigned(j,3);
                wait for 10 ns; 
            end loop;
        end loop;   
   end process;

END;

A part of the simulation waveform is given below: