Thursday, 15 November 2012

VHDL Tutorials: Decoder 2x4

|0 comments
Behavior Code : ------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------- entity DECODER is port( I: in std_logic_vector(1 downto 0); O: out std_logic_vector(3 downto 0) ); end DECODER; ------------------------------------------------- architecture behv of DECODER is begin -- process statement process (I) begin -- use case...[Readmore]

Wednesday, 7 November 2012

VHDL Tutorials:Combinational Logic

|1 comments
Combinational Logic Design Behavioral Code: library ieee; -- component #1 use ieee.std_logic_1164.all; entity OR_GATE is port( X: in std_logic; Y: in std_logic; F2: out std_logic ); end OR_GATE; architecture behv of OR_GATE is begin process(X,Y) begin F2 <= X or Y; -- behavior des. end process; end behv; ------------------------------------------------------------- library ieee; -- component #2 use ieee.std_logic_1164.all; entity...[Readmore]