VHDL Tutorials: Hardware Abstraction

Hardware Abstraction

   VHDL is used to describe a model for a digital hardware device. This model specifies the external view of the device and one or more internal views. The internal view of the device specifies the functionality or structure, while the external view specifies the interface of the device through which it communicates with the other models in its environment. Figure I.I shows the hardware device and the corresponding software model.

The device to device model mapping is strictly a one to many. That is, a hardware device may have many device models. For example, a device modeled at a high leyel of abstraction may not have a clock as one of its inputs, since the clock may not have been used in the description. Also the data transfer at the interface may be treated in terms of say, integer values, instead of logical values. In VHDL, each device model is treated as a distinct representation of a unique device, called an entity in this text. Figure 1.2 shows the VHDL view of a hardware device that has multiple device models, with each device model representing one entity. Even though entity I through N represent N different entities from the VHDL point of view, in reality they represent the same hardware device.

Figure 1.2 A VHDL view of a device

   The entity is thus a hardware abstraction of the actual hardware device. Each entity is described using one model that contains one external view and one or more internal views. At the same time, a hardware device may be represented by one or more entities.

VHDL Tutorials: Program for 4x1 Multiplexer

   The Program for a 4x1 Multipexer using CASE statement is :

use IEEE.std_logic_1164.all;


-- this is the entity

entity MUX is
port (A, B, C, D: in BIT; CTRL: in BIT_VECTOR(0 to 1);
Z: out BIT);
end MUX;

-- this is the architecture
architecture MUX_BEHAVIOR of MUX is
constant MUX_DELAY: TIME := 10 ns;
begin
PMUX: process (A, B, C, D, CTRL)
variable TEMP: BIT;
begin
case CTRL is
when "00" => TEMP := A:
when "01" => TEMP := B;
when "10" => TEMP := C;
when "11" => TEMP := D;
end case;
Z <= TEMP after MUX_DELAY;
end process PMUX;
end MUX_BEHAVIOR;

  The simulated testbench waveform is shown below:

 The code was synthesized using XILINX ISE XST . The RTL schematic of the design is shown below.

VHDL Tutorials: Program for AND Gate

   Here is the Program for AND GATE is :
 
-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
 
-- this is the entity
entity ANDGATE is
  port ( 
    I1 : in std_logic;
    I2 : in std_logic;
    O  : out std_logic);
end entity ANDGATE;
 
-- this is the architecture
architecture RTL of ANDGATE is
begin
  O <= I1 and I2;
end architecture RTL;

Generally, simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as the std_logic type might at first seem to be an overkill. One could easily use the built-in bit type and avoid the library import in the beginning. However, using this 9-valued logic (U,X,0,1,Z,W,H,L,-) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.


Simulation Picture for And Gate Using VDHL:

VHDL Tutorial : Mixed Style of Modeling

4. Mixed Style of Modeling

1.FULL ADDER

   It is possible to mix the three modeling styles that we have seen so far in a single architecture body. That is, within an architecture body, we could use component instantiation statements (that represent structure), concurrent signal assignment statements (that represent dataflow), and process statements (that represent behavior). Here is an example of a mixed style model for a one-bit full-adder shown in Fig. 2.7.

entity FULL_ADDER is

port (A, B, CIN: in BIT; SUM, COUT: out BIT);

end FULL_ADDER;

architecture FA_MIXED of FULL_ADDER is

component XOR2

port (A, B: in BIT; Z: out BIT);

end component;

signal S1: BIT;

begin

X1: XOR2 port map (A, B, S1 ); - structure.

process (A, B, CIN) - behavior.

variable T1, T2, T3: BIT;

begin

T1 :=A and B;

T2 := B and CIN;

T3:=A and CIN;

COUT <= T1 or T2 or T3;

end process;

SUM <= S1 xor CIN; - dataflow.

end FA_M!XED;

Figure 2.7 A 1-bit full-adder

   The full-adder is represented using one component instantiation statement, one process statement and one concurrent signal assignment statement. All of these statements are concurrent statements, and therefore, their order of appearance within the architecture body is not important. Note that a process statement itself is a concurrent statement; however, statements within a process statement are always executed sequentially. SI is a signal locally declared within the architecture body and is used to pass the value from the output of the component XI to the expression for signal SUM.

VHDL Tutorial : Behavioral Style of Modeling

3. Behavioral Style of Modeling

1. DECODER2x4

In contrast to the styles of modeling described earlier, the behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order. This set of sequential statements, that are specified inside a process statement, do not explicitly specify the structure of the entity but merely specifies its functionality. A process statement is a concurrent statement that can appear within an architecture body. For example, consider the following behavioral model for the DECODER2x4 entity.

architecture DEC_SEQUENTIAL of DECODER2x4 is 

begin 

process (A, B, ENABLE)

variable ABAR, BBAR: BIT; 

begin

ABAR := not A;                                             - statement 1 

BBAR := not B;                                              - statement 2 

if (ENABLE = '1') then                                    -statements 

Z(3) <= not (A and B):                                    - statement 4 

Z(0) <= not (ABAR and BBAR);                    -statement 5 

Z(2) <= not (A and BBAR);                            - statement 6 

Z(1 ) <= not (ABAR and B);                           - statement 7 

else

Z<= "1111";                                                   -statement 8

end if; 

end process; 

end;

 Figure 2.4 A 2-to-4 decoder circuit

   A process statement, too, has a declarative part (between the keywords process and begin), and a statement part (between the keywords begin and end process). The statements appearing within the statement part are sequential statements and are executed sequentially. The list of signals specified within the parenthesis after the keyword process constitutes a sensitivity list and the process statement is invoked whenever there is an event on any signal in this list. In the previous example, when an event occurs on signals A, B, or ENABLE, the statements appearing within the process statement are executed sequentially.

The variable declaration (starts with the keyword variable) declares two variables called ABAR and BBAR. A variable is different from a signal in that it is always assigned a value instantaneously and the assignment operator used is the := compound symbol; contrast this with a signal that is assigned a value always after a certain delay (user-specified or the default delta delay), and the assignment operator used to assign a value to a signal is the <= compound symbol. Also, variables can only be declared within a process and their scope is limited to that process (variables can also be declared in subprograms). Note, however, that signals cannot be declared within a process.

   Signal assignment statements appearing within a process are called sequential signal assignment statements. Sequential signal assignment statements, including variable assignment statements, are executed sequentially independent of whether an event occurs on any signals in its right-hand-side expression or not; contrast this with the execution of concurrent signal assignment statements in the dataflow modeling style. In the previous architecture body, if an event occurs on any signal. A, B, or ENABLE, statement I which is a variable assignment statement, is executed, then statement 2 is executed, and so on. Execution of the third statement, an if statement, causes control to jump to the appropriate branch based on the value of the signal, ENABLE. If the value of ENABLE is 1', the next four signal assignment statements, 4 through 7, are executed independent of whether A, B, ABAR, or BBAR changed values, and the target signals are scheduled to get their respective values after delta delay. If ENABLE has a value '0', a value of 'V is assigned to each of the elements of the output array, Z. When execution reaches the end of the process, the process suspends itself, and waits for another event to occur on a signal in its sensitivity list.

2.CLOCK

   It is possible to use case or loop statements within a process. The semantics and structure of these statements are very similar to those in other high-level programming languages like C or Pascal. An explicit wait statement can also be used to suspend a process. It can be used to wait for a certain amount of time or to wait until a certain condition becomes true, or to wait until an event occurs on one or more signals. Here is an example of a process statement that generates a clock with a different on-off period. Figure 2.6 shows the generated waveform.

process

begin

CLK <= '0' ;

wait for 20 ns;

CLK <= '1' ;

wait for 12 ns;

end process;

Figure 2.6 A clock waveform with varying on-off period

This process does not have a sensitivity list since explicit wait statements are present inside the process. It is important to remember that a process never terminates. It is always either being executed or in a suspended state. All processes are executed once during the initialization phase of simulation until they get suspended. Therefore, a process with no sensitivity list and with no explicit wait statements will never suspend itself.

3. D FLIP-FLOP

A signal can represent not only a wire but also a place holder for a value, that is, it can be used to model a flip-flop. Here is such an example. Port signal Q models a level-sensitive flip-flop.

entity LS_DFF is

port (Q: out BIT; D, CLK: in BIT):

end LS_DFF;

architecture LS_DFF_BEH of LS_DFF is

begin

process (D, CLK)

begin

if (CLK = '1') then

Q <= D;

end if;

end process;

end LS_DFF_BEH;

VHDL Tutorial : Dataflow Style of Modeling

2.Dataflow Style of Modeling

1.HALF ADDER

   In this modeling style, the flow of data through the entity is expressed primarily using concurrent signal assignment statements. The structure of the entity is not explicitly specified in this modeling style, but it can be implicitly deduced. Consider the following alternate architecture body for the HALF..ADDER entity that uses this style.

architecture HA_CONCURRENTof HALF_ADDER is

begin

SUM <= A xor B after 8 ns;

CARRY <= A and B after 4 ns;

end HA_CONCURRENT;

Figure 2.3 A half-adder circuit

   The dataflow model for the HALF_ADDER is described using two concurrent signal assignment statements (sequential signal assignment statements are described in the next section). In a signal assignment statement, the symbol <= implies an assignment of a value to a signal. The value of the expression on the right-hand-side of the statement is computed and is assigned to the signal on the left-hand-side, called the target signal. A concurrent signal assignment statement is executed only when any signal used in the expression on the right-hand-side has an event on it, that is, the value for the signal changes.

Delay information is included in the signal assignment statements using after clauses. If either signal A or B, which are input port signals of HALF_ADDER entity, has an event, say at time T, the right-hand-side expressions of both signal assignment statements are evaluated. Signal SUM is scheduled to get the new value after 8 ns while signal CARRY is scheduled to get the new value after 4 ns. When simulation time advances to (T+4) ns, CARRY will get its new value and when simulation time advances to (T+8) ns, SUM will get its new value. Thus, both signal assignment statements execute concurrently.

Concurrent signal assignment statements are concurrent statements, and therefore, the ordering of these statements in an architecture body is not important. Note again that this architecture body, with name HA_CONCURRENT, is also associated with the same HALF_ADDER entity declaration.

2.DECODER2x4

Here is a dataflow model for the DECODER2x4 entity.

architscture dec_dataflgw of DECODER2x4 is

signal ABAR, BBAR: BIT;

begin

Z(3) <= not (A and B and ENABLE); - statement 1

Z(0) <= not (ABAR and BBAR and ENABLE); - statement 2

BBAR <= not B; - statement 3

Z(2) <= not (A and BBAR and ENABLE); - statement 4

ABAR <= not A; - statement 5

Z(1 ) <= not (ABAR and B and ENABLE); - statement 6

end DEC_DATAFLOW;

 Figure 2.4 A 2-to-4 decoder circuit

   The architecture body consists of one signal declaration and six concurrent signal assignment statements. The signal declaration declares signals ABAR and BBAR to be used locally within the architecture body. In each of the signal assignment statements, no after clause was used to specify delay. In all such cases, a default delay of 0ns is assumed. This delay of 0ns is also known as delta delay, and it represents an infinitesimally small delay. This small delay corresponds to a zero delay with respect to simulation time and does not correspond to any real simulation time.

3.CLOCK

   To understand the behavior of this architecture body, consider an event happening on one of the input signals, say input port B at time T. This would cause the concurrent signal assignment statements 1,3, and 6, to be triggered. Their right-hand-side expressions would be evaluated and the corresponding values would be scheduled to be assigned to the target signals at time (T+A). When simulation time advances to (T+A), new values to signals Z(3), BBAR, and Z(1), are assigned. Since the value of BBAR changes, this will in turn trigger signal assignment statements, 2 and 4. Eventually, at time (T+2A), signals Z(0) and Z(2) will be assigned their new values.

   The semantics of this concurrent behavior indicate that the simulation, as defined by the language, is event-triggered and that simulation time advances to the next time unit when an event is scheduled to occur. Simulation time could also advance a multiple of delta time units. For example, events may have been scheduled to occur at times 1,3,4,4+A, 5,6,6+A, 6+2A, 6+3A, 10,10+A, 15, 15+A time units.

The after clause may be used to generate a clock signal as shown in the following concurrent signal assignment statement

CLK <= not CLK after 10 ns;

   This statement creates a periodic waveform on the signal CLK with a time period of 20 ns as shown in Fig. 2.5.

Figure 2.5 A clock waveform with constant on-off period

VHDL Tutorial : Structural Style of Modeling

Architecture Body

   The internal details of an entity are specified by an architecture body using any of the following modeling styles:

1. As a set of interconnected components (to represent structure),

2. As a set of concurrent assignment statements (to represent dataflow),

3. As a set of sequential assignment statements (to represent be-hav.ior),

4. Any combination of the above three.

1. Structural Style of Modeling

1.HALF ADDER

   In the structural style of modeling, an entity is described as a set of interconnected components. Such a model for the HALF_ADDER entity, shown in Fig. 2.3, is described in an architecture body as shown below.

architecture HA_STRUCTURE of HALF_ADDER is

component XOR2

port (X, Y: in BIT; Z: out BIT);

end component;

component AND2

port (L, M: in BIT; N: out BIT);

end component;

begin

X1: XOR2 port map (A, B, SUM);

A1: AND2 port map (A, B, CARRY);

end HA_STRUCTURE;

Figure 2.3 A half-adder circuit

The name of the architecture body is HA_STRUCTURE. The entity declaration for HALF_ADDER (presented in the previous section) specifies the interface ports for this architecture body. The architecture body is composed of two parts: the declarative part (before the keyword begin) and the statement part (after the keyword begin). Two component declarations are present in the declarative part of the architecture body. These declarations specify the interface of components that are used in the architecture body. The components XOR2 and AND2 may either be predefined components in a library, or if they do not exist, they may later be bound to other components in a library.

The declared components are instantiated in the statement part of the architecture body using component instantiation statements. XI and A1 are the component labels for these component instantiations. The first component instantiation statement, labeled XI, shows that signals A and B (the input ports of the HALF_ADDER), are connected to the X and Y input ports of a XOR2 component, while output port Z of this component is connected to output port SUM of the HALF_ADDER entity.

Similarly, in the second component instantiation statement, signals A and B are connected to ports L and M of the AND2 component, while port N is connected to the CARRY port of the HALF_ADDER. Note that in this case, the signals in the port map of a component instantiation and the port signals in the component declaration are associated by position (called positional association). The structural representation for the HALF_ADDER does not say anything about its functionality. Separate entity models would be described for the components XOR2 and AND2, each having its own entity declaration and architecture body.

2.DECODER2x4

   A structural representation for the DECODER2x4 entity, shown in Fig. 2.4, is shown next.

architecture DEC_STR of DECODER2x4 is

component INV

port (A: in BIT; Z: out BIT);

end component;

component NAND3

port (A, B, C: in BIT; Z: out BIT);

end component;

signal ABAR, BBAR: BIT;

begin

I0: INV port map (A, ABAR);

I1: INV port map (B, BBAR);

N0: NAND3 port map (ABAR, BBAR, ENABLE, Z(0));

N1: NAND3 port map (ABAR, B, ENABLE, Z(1));

N2: NAND3 port map (A, BBAR, ENABLE, Z(2));

N3: NAND3 port map (A, B, ENABLE, Z(3));

end DEC_STR;

 Figure 2.4 A 2-to-4 decoder circuit

   In this example, the name of the architecture body is DEC_STR, and it is associated with the entity declaration with the name DECODER2x4; therefore, it inherits the list of interface ports from that entity declaration. In addition to the two component declarations (for INV and NAND3), the architecture body contains a signal declaration that declares two signals, ABAR and BBAR, of type BIT. These signals, that represent wires, are used to connect the various components that form the decoder. The scope of these signals is restricted to the architecture body, and therefore, these signals are not visible outside the architecture body. Contrast these signals with the ports of an entity declaration that are available for use within any architecture body associated with the entity declaration.

A component instantiation statement is a concurrent statement, as defined by the language. Therefore, the order of these statements is not important. The structural style of modeling describes only an interconnection of components (viewed as black boxes) without implying any behavior of the components themselves, nor of the entity that they collectively represent. In the architecture body DEC_STR, the signals A, B, and ENABLE, used in the component instantiation statements are the input ports declared in the DECODER2x4 entity declaration. For example, in the component instantiation labeled N3, port A is connected to input A of component NAND3, port B is connected to input port B of component NAND3, port ENABLE is connected to input port C, and the output port Z of component NAND3 is connected to port Z(3) of the DECODER2x4 entity. Again positional association is used to map signals in a port map of a component instantiation with the ports of a component specified in its declaration. The behavior of the components NAND3 and INV are not apparent, nor is the behavior of the decoder entity that the structural model represents.

VHDL Tutorial : Entity Declaration

Entity Declaration

   The entity' declaration specifies the name of the entity being modeled and lists the set of interface ports. Ports are signals through which the entity communicates with the other models in its external environment.

Figure 2.3 A half-adder circuit

Here is an example of an entity declaration for the half-adder circuit shown in Fig. 2.3.

entity HALF_ADDER is

port (A, B: in BIT; SUM, CARRY: out BIT); end HALF_ADDER;

-- This is a comment line.

   The entity, called HALF_ADDER, has two input ports, A and B (the mode in specifies input port), and two output ports, SUM and CARRY (the mode out specifies output port). BIT is a predefined type of the language; it is an enumeration type containing the character literals '0' and '1'. The port types for this entity have been specified to be of type BIT, which means that the ports can take the values, '0' or '1'.

The following is another example of an entity declaration for a 2-to-4 decoder circuit shown in Fig. 2.4.

entity DECODER2x4 is

port (A, B, ENABLE: in SIT: Z: out BIT_VECTOR(0 to 3)); end DECODER2x4;

 Figure 2.4 A 2-to-4 decoder circuit

 This entity, called DECODER2x4, has three input ports and four output ports. BIT_VECTOR is a predefined unconstrained array type of BIT. An unconstrained array type is a type in which the size of the array is not specified. The range "0 to 3" for port Z specifies the array size.

   From the last two examples of entity declarations, we see that the entity declaration does not specify anything about the internals of the entity. It only specifies the name of the entity and the interface ports.

VHDL Tutorial :Basic Terminology

Basic Terminology

   VHDL is a hardware description language that can be used to model a digital system. The digital system can be as simple as a logic gate or as complex as a complete electronic system. A hardware abstraction of this digital system is called an entity in this text. An entity X, when used in another entity Y, becomes a component for the entity Y. Therefore, a component is also an entity, depending on the level at which you are trying to model.

   To describe an entity, VHDL provides five different types of primary constructs, called" design units.

They are

1.  Entity declaration

2.  Architecture body

3.  Configuration declaration

4.  Package declaration

5.  Package body

   An entity is modeled using an entity declaration and at least one architecture body. The entity declaration describes the external view of the entity, for example, the input and output signal names. The architecture body contains the internal description of the entity, for example, as a set of interconnected components that represents the structure of the entity, or as a set of concurrent or sequential statements that represents the behavior of the entity. Each style of representation can be specified in a different architecture body or mixed within a single architecture body Figure 2.1 shows an entity and its model.

Figure 2.1 An entity and its model

   A configuration declaration is used to create a configuration for an entity. It specifies the binding of one architecture body from the many architecture bodies that may be associated with the entity. It may also specify the bindings of components used in the selected architecture body to other entities. An entity may have any number of different configurations.

A package declaration encapsulates a set of related declarations such as type declarations, subtype declarations, and subprogram declarations that can be shared across two or more design units. A package body contains the definitions of subprograms declared in a package declaration.

Figure 2.2 shows three entities called El, E2, and E3. Entity El has three architecture bodies, EI_AI, EI_A2, and EI_A3. Architecture body EI_AI is a purely behavioral model without any hierarchy. Architecture body EI_A2 uses a component called BX, while architecture body EI_A3 uses a component called CX. Entity E2 has two architecture bodies, E2_AI and E2_A2, and architecture body E2_AI uses a component called MI. Entity E3 has three architecture bodies, E3_AI, E3_A2, and E3_A3. Notice that each entity has a single entity declaration but more than one architecture body.

The dashed lines represent the binding that may be specified in a configuration for entity El. There are two types of binding shown: binding of an architecture body to its entity and the binding of components used in the architecture body with other entities. For example, architecture body, EI_A3, is bound to entity El, while architecture body, E2_AI, is bound to entity E2. Component MI in architecture body, E2_AI, is bound to entity E3. Component CX in the architecture body, EI_A3, is bound to entity E2. However, one may choose a different configuration for entity El with the following bindings:

•   Architecture EI_A2 is bound to its entity El

•  Component BX to entity E3

•  Architecture E3_AI is bound to its entity E3

Figure 2.2 A configuration for entity El

   Once an entity has been modeled, it needs to be validated by a VHDL system. A typical VHDL system consists of an analyzer and a simulator. The analyzer reads in one or more design units contained in a single file and compiles them into a design library after validating the syntax and performing some static semantic checks. The design library is a place in the host environment (that is, the environment that supports the VHDL system) where compiled design units are stored.

   The simulator simulates an entity, represented by an entity-architecture pair or by a configuration, by reading in its compiled description from the design library and then performing the following steps:

1. Elaboration

2. Initialization

3. Simulation

   A note on the language syntax. The language is casc-iriSRissitive, that is, lower-case and upper-case characters are treated alike. For example, CARRY, CarrY, or CarrY, all refer to the same name. The language is also free -format, very much like in Ada and Pascal programming languages. Comments are specified in the language by preceding the text with two consecutive dashes (-). All text between the two dashes and the end of that line is treated as a comment.